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The Computer Journal 1972 15(3):254-258; doi:10.1093/comjnl/15.3.254
© 1972 by British Computer Society
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Ternary logic in parallel multipliers*

Z. G. Vranesic § and V. C. Hamacher §

Department of Electrical Engineering and Computer Science, University of Toronto, Toronto, Ontario, Canada

The logic cost and speed of parallel multipliers implemented in both binary and ternary logic is studies. Binary operand lengths of 8 through 32 bits and the corresponding ternary digit range of 6 through 21 are considered. For the particular design technique used, the binary versions are slightly faster where the speed criterion is in terms of the longest logic path from operands to product. Ternary designs show smaller total cost of gates and a major reduction in the number of required inputs, indicating greatly simplified wiring interconnection complexity.

Received June 1971.

* This Research was supported in part by the National Research Council of Canada

§ Departments of Electrical Engineering and Computer Science, University of Toronto, Toronto, Ontario, Canada


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