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The Computer Journal 1976 19(3):254-257; doi:10.1093/comjnl/19.3.254
© 1976 by British Computer Society
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Analysis of speed of a binary multiplier using a variable number of shifts per cycle

M. R. Patel * and K. H. Bennett

Department of Computer Science, University of Keele, Keele, UK

Iterative binary multiplication can be speeded up by examining two or more bits of the multiplier in each cycle. Freeman (1967) has described an exact method for calculating the resultant gain in multiplication speed, based on the use of a discrete-time finite state system model. We have used Freeman's model to evaluate the gain in speed for various combinations of two design parameters—the maximum number of shifts per cycle, and the available multiples of the multiplicand. It is shown that a greater performance improvement is obtained by increasing the former parameter rather than the latter.

Received February 1975.

* International Computers Limited.

§ Department of Computer Science, University of Keele, Keele, Staffordshire ST5 5BG


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