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The Computer Journal 1978 21(1):73-78; doi:10.1093/comjnl/21.1.73
© 1978 by British Computer Society
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Some improved designs for the digital summation threshold logic (DSTL) gate

C. R. Edwards *

School of Electrical Engineering, University of Bath, Claverton Down, Bath, UK

Some computer-generated improved designs for the digital summation threshold logic gate, first described by Hurst, are presented. These designs require considerably fewer logic elements than the original designs and have improved gate-delay parameters. The improved designs are shown to have delay times comparable to those of the ‘bifurcated’ gates of Reddy and Swamy, whilst enjoying a more elegant structure. Some implementations for these circuits are given.

Received November 1976.

* School of Electrical Engineering, University of Bath, Claverton Down, Bath BA2 7AY


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