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The Computer Journal 1978 21(3):246-252; doi:10.1093/comjnl/21.3.246
© 1978 by British Computer Society
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Analysis of speed of a binary divider using a variable number of shifts per cycle

M. R. Patel * and K. H. Bennett *

International Computers Limited and the Computer Science Department, University of Keele, UK

In a recent paper (1976), the analysis of a binary multiplier using a variable number of shifts per multiplication cycle was described. The method was based on a discrete time finite state system model. In this paper we continue the analysis for the more complex case of binary division. The results enable the optimum hardware configuration to be determined for a given cost.

Received January 1977.

* The authors are respectively with International Computers Limited and the Computer Science Department, University of Keele, Staffs, ST5 5BG


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