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The Computer Journal 1979 22(2):169-172; doi:10.1093/comjnl/22.2.169
© 1979 by British Computer Society
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Generation of shortest test sequences for detecting individual faults of sequential circuits

S. S. Yau * and Y. S. Tang *

Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, Illinois, USA

A technique for generating the shortest test sequences to detect individual faults of synchronous sequential circuits is presented. Instead of working on the flow table of a sequential machine, this technique deals with the logic equations of the given circuit of a sequential machine. It is based on the manipulation of the output functions expressed in terms of the primary input variables and the fault under consideration. The types of faults considered are single stuck-at-0 and stuck-at-1 faults. It is quite efficient and applicable to synchronous sequential circuits with or without reset circuitry. The effect of undetectable faults on this technique is also discussed.

Received October 1975.

* Now with Bell Telephone Laboratories, Naperville, Illinois, USA


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