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The Computer Journal 1984 27(3):254-259; doi:10.1093/comjnl/27.3.254
© 1984 by British Computer Society
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Architectural Considerations of the Parallel SIMULA Machine

M. P. Papazoglou1 * §, P. I. Georgiadis2 ¶ and D. G. Maritsas2 ¶

1 University of Dundee Department of Electronics and Microprocessors, Dundee, UK, 2 University of Patras, Department of Computer Science, Patras, Greece

The development of problem-oriented hardware has become a possibility as a result of current technological advances. New machine architectures can now be defined, reflecting the high performance requirements which are set by specific application areas. Large-scale discrete time simulation is a problem area which demands high-speed processing, especially within the realm of real-time applications. The natural parallelism which characterizes many real-life dynamic systems and remains unexploited in the environment of uniprocessor machines, points decisively towards multiprocessor structures. Although the process-oriented simulation languages have proved very effective in accommodating this kind of parallelism in the corresponding simulation programs, their execution in the uniprocessor machines reverts the situation back to the unhappy reality of serial execution of otherwise independent tasks. SIMULA-67 is a process-oriented language specifically designed for advanced and complex software simulation products. The process structure of SIMULA allows for the definition of concurrent tasks within a SIMULA program which can be executed in parallel within the environment of a multiprocessor system. The analysis and the basic software architectural scheme for a parallel SIMULA machine (PSM) have already been reported by the authors in a previous paper. In the present paper a hardware organization of a PSM is presented. A system architecture is explored which is conceived so as to implement efficiently the execution algorithm (process co-ordination and synchronization algorithm) which has been outlined by the authors in previous papers. The architecture is based upon the master/slave system topology. It incorporates a central controller microprocessor and a number of satellite microprocessors. The interconnection circuitry between the microprocessor and a number of satellite microprocessors. The interconnection circuitry between the microprocessor modules involves a time-sharing system bus and various programmable interrupt control units. Common and private memory modules reside in the system, and DMA transfers are employed to alleviate the controller's workload. The time operational features of the parallel SIMULA machine are also described.

Received June 1983.

* Present address: University of Patras, Department of Computer Sciences, Patras, Greece.

§ University of Dundee Department of Electronics and Microprocessors, Dundee, UK

University of Patras, Department of Computer Science, Patras, Greece


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