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The Computer Journal 1989 32(5):461-469; doi:10.1093/comjnl/32.5.461
© 1989 by British Computer Society
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Principles For the Design of a Distributed Memory Architecture for Parallel Graph Reduction*

D. I. Bevan, G. L. Burn §, R. J. Karia and J. D. Robson §

GEC Hirst Research Centre, East Lane, Wembley, Middlesex, HA9 7PP, UK

Many models for the parallel reduction of lazy functional languages have been proposed in the literature. The one we have chosen to implement is based on evaluation transformers. An evaluation transformer says how much evaluation can be done to an argument expression in a function application, given the amount of evaluation that can be done to the application.

Rather than just selecting a distributed memory architecture and trying to support parallel graph reduction, we investigate the implications of a minimally specified distributed memory architecture for parallel graph reduction.

The results of the investigation are incorporated into an abstract machine which is able to support the communication and synchronisation needs of the parallel reduction model on a distributed memory architecture. Certain flags are needed on the nodes in the program graph in order to support the model. These are motivated and described.

Received July 1987. revised October 1988.

* This work was partially funded by ESPRIT Project 415: Parallel Languages and Architectures for AIP – VLSI-directed Approach.

§ Electronic mail addresses: geoff{at}uk.co.gec-rl-hrc; jdr{at}uk.co.gec-rl-hrc.

GEC Hirst Research Centre, East Lane, Wembley, Middlesex, HA9 7PP


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