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The Computer Journal 1991 34(4):290-300; doi:10.1093/comjnl/34.4.290
© 1991 by British Computer Society
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The HDG-machine: a highly distributed graph-reducer for a transputer network*

H. Kingdon, D. R. Lester § and G. L. Burn

GEC-Marconi Ltd. Hirst Research Centre, East Lane, Wembley, HA9 7PP, UK

Distributed implementations of programming languages with implicit parallelism hold out the prospect that the parallel programs are immediately scalable. This paper presents some of the results of our part of Esprit 415, in which we considered the implementation of lazy functional programming languages on distributed architectures.

A compiler and abstract machine were designed to achieve this goal. The abstract parallel machine was formally specified, using Miranda. Each instruction of the abstract machine was then implemented as a macro in the Transputer Assembler. Although macro expansion of the code results in non-optimal code generation, use of the Miranda specification makes it possible to validate the compiler before the Transputer code is generated.

The hardware currently available consists of five T800-25s, each board having 16 Mbytes of memory. Benchmark timings using this hardware are given. In spite of the straightforward code-generation, the resulting system compares favourably with more sophisticated sequential implementations, such as that of LML.

Received September 1990.

* Research under taken while the author were employed by GEC Hirst Research Center, and partially funded by ESPRIT Project 425: ‘Parellel Architectures and Languages for AIP-A VLSI-Directed Approach’.

§ TO whom all enquiries about this paper should be addressed


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