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The Computer Journal 1993 36(8):763-777; doi:10.1093/comjnl/36.8.763
© 1993 by British Computer Society
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The MP1 Network Chip and its Application to Parallel Computers

C. R. Jesshope1 * and C. Izu2 §

1 Department of Electronic and Electrical Engineering, The University of Surrey, Guildford, Surrey GU2 5XH, UK, 2 Department of Computer Architecture and Technology, University of the Basque Country, 649 p.k E-20080 Donostia, Spain

This paper presents results concerning the design and testing of a fast network chip (the MP1) for parallel computers. We briefly introduce the theoretical results on which the MP1 chip design was based and describe its architecture. The chip has been fabricated and tested in small prototype system. Based on parameters measured using this prototype and a simulator implemented at the logic level we have been able to accurately model the performance of larger networks based on this chip under a variety of synthetic loads. Extensive results are presented based on these simulations.

Received June 1993. revised September 1993.

* Department of Electronic and Electrical Engineering, The University of Surrey, Guildford, Surrey GU2 5XH, UK

§ Department of Computer Architecture and Technology, University of the Basque Country, 649 p.k E-20080 Donostia, Spain


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