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The Computer Journal 1994 37(7):610-620; doi:10.1093/comjnl/37.7.610
© 1994 by British Computer Society
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Stack Cache Memory for Block-Structured Programs

L. Lopriore *

Dipartimento di Ingegneria della Informazione: Elettronica, Informatica, Telecomunicazioni, Universita degli Studi di Pisa, via Diotisalvi 2, 56126 Pisa, Italy

The architecture of a cache memory is presented, aimed at reducing the memory bandwidth requirements of programs written in block-structured, high-level languages. At any given time, the cache contains two portions of the stack area of the running program, corresponding to the global and the local activation records. With respect to traditional cache architectures, the proposed architecture is characterized by increased performance and a reduced complexity of the logic for cache space addressing and management. These results have been obtained by controlling the cache activity at the software level to take advantage of the stack paradigm.

Received December 1993. revised May 1994.

* Dipartimento di Ingegneria della Informazione: Elettronica, Informatica, Telecomunicazioni, Università degli Studi di Pisa, via Diotisalvi 2, 56126 Pisa, Italy


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