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The Computer Journal 1997 40(6):356-372; doi:10.1093/comjnl/40.6.356
© 1997 by British Computer Society
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Compile-Time Scheduling Algorithms for a Heterogeneous Network of Workstations

M. Cierniak, M. J. Zaki and W. Li

Computer Science Department, University of Rochester, Rochester, NY 14627, USA Email: zaki{at}cs.rochester.edu

In this paper, we study the problem of scheduling parallel loops at compile time for a heterogeneous network of workstations. We consider heterogeneity in various aspects of parallel programming: program, processor, memory and network. A heterogeneous program has parallel loops with different amounts of work being done in each iteration; heterogeneous processors have different speeds; heterogeneous memory refers to the different amounts of user-available memory on the machines and a heterogeneous network has different communication costs between processors. We propose a simple yet comprehensive model for use in compiling for a network of processors, and develop compiler algorithms for generating optimal and near-optimal schedules of loops for load balancing, communication optimizations, network contention and memory heterogeneity. Experiments show that a significant performance improvement is achieved using our techniques.

Received October 31, 1996. revised July 15, 1997.


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