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The Computer Journal 1998 41(1):45-51; doi:10.1093/comjnl/41.1.45
© 1998 by British Computer Society
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Logic Design of a Fast Circuit for Iterative Additions in Redundant Hybrid Number Systems

G. Alia1 and E. Martinelli2

1 Dipartimento di Ingegneria dell'Informazione, Università di Pisa, Via Diotisalvi, 2, 56126 Pisa, Italy Email: alia{at}iet.unipi.it, 2 Dipartimento di Ingegneria dell'Informazione, Università di Siena, Via Roma, 56, 53100 Siena, Italy

Repeated modular additions and overflow detection are possible in redundant hybrid number systems (RHNS). In this paper a circuit is proposed that implements the overflow-detecting procedure in such systems and allows a mean addition time of about 10.5 gate delays for numbers having a magnitude order normally distributed in the range [–233, 233 – 1], versus a 14 gate delay required by 32-bit CLA adders.

Received November 27, 1995. revised December 11, 1997.


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