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The Computer Journal 2000 43(2):138-151; doi:10.1093/comjnl/43.2.138
© 2000 by British Computer Society
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Data Placement Schemes to Reduce Conflicts in Interleaved Memories

Lizy Kurian John1

1 Electrical and Computer Engineering Department, University of Texas at Austin, Austin, TX 78712, USA, USA Email: ljohn@ece.utexas.edu

In interleaved memories, interference between concurrently active vector streams results in memory bank conflicts and reduced bandwidth. In this paper, we present two schemes for reducing inter-vector interference. First, we propose a memory module partitioning technique in which disjoint access sets are created for each of the concurrent vectors. Various properties of the involved address mapping are presented. Then we present an interlaced data placement scheme, where the simultaneously accessed vectors are interlaced and stored in the memory. The performance of the two schemes is evaluated by simulation. It is observed that the schemes have significant merit in reducing the interference in interleaved memories and increasing the effective memory bandwidth. The schemes are applicable to memory systems for superscalar microprocessors, vector supercomputers and parallel processors.

Received 11 August, 1998. Revised 4 January, 2000.


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