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The Computer Journal 2004 47(1):71-84; doi:10.1093/comjnl/47.1.71
© 2004 by British Computer Society
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Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs)

Ying Xu1,, Xiaoyu Song2,§, Eduard Cerny3,¶ and Otmane Ait Mohamed4,{ddagger}

1 Nortel Networks, Ottawa, Canada 2 Department of ECE, Portland State University, Portland, OR, USA 3 D'IRO, Université de Montreal, Montreal, Canada 4 Department of ECE, University of Concordia, Montreal, Canada

We study model checking for a first-order linear-time temporal logic. We present the computation model: abstract description of state machines (ASMs), in which data and data operations are described using abstract sort and uninterpreted function symbols. ASMs are suitable for describing Register Transfer level designs. We define a first-order linear-time temporal logic called LMDG which supports the abstract data representations. Both safety and liveness properties can be expressed in LMDG, however, only universal path quantification is possible. Fairness constraints can also be imposed. The property checking algorithms are based on implicit state enumeration of an ASM and implemented using Multiway Decision Graphs.

Received 26 March 2002. Revised 20 June 2003.

* Email: xuying{at}nortelnetworks.com

§ Email: song{at}ee.pdx.edu

Email: cerny{at}iro.umontreal.ca

{ddagger} Email: ait{at}ece.concordia.ca


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