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The Computer Journal 2004 47(1):93-102; doi:10.1093/comjnl/47.1.93
© 2004 by British Computer Society
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A Suggestion for a Fast Residue Multiplier for a Family of Moduli of the Form (2n – (2p ± 1))

Ahmad A. Hiasat

Electronics Engineering Department, Princess Sumaya University, PO Box 1438, Amman 11941, Jordan

The family of moduli that has the form (2n – (2p ± 1)) is considered in this paper. A suggestion for a fast residue multiplier for this family of moduli is introduced. The multiplication algorithm proposed in this paper generates (2n + p – 2) partial products; however, it compresses the magnitude of each partial product to be less than 2n. Although it requires an additional integrated circuit area compared with the most recent published study, the new proposed modular multiplier has a logarithmic delay, which makes it faster than any other modular multiplier. Moreover, it is even faster than binary-based iterative array multipliers with a final CLA addition. The proposed modular multiplier is very suitable for medium and large dynamic ranges.

Received 8 August 2002. Revised 10 March 2003.

* Email: aahiasat{at}psut.edu.jo


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