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The Computer Journal Advance Access originally published online on August 17, 2006
The Computer Journal 2007 50(1):81-92; doi:10.1093/comjnl/bxl048
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© The Author 2006. Published by Oxford University Press on behalf of The British Computer Society. All rights reserved. For Permissions, please email: journals.permissions@oxfordjournals.org

A Fast Radix-4 Floating-Point Divider with Quotient Digit Selection by Comparison Multiples

Hooman Nikmehr1,2,*, Braden Phillips1 and Cheng-Chew Lim1

1 School of Electrical and Electronic Engineering, The University of Adelaide Adelaide 5005, Australia
2 Department of Computer Engineering, Bu Ali Sina University Hamedan, Iran

*Corresponding author: nhooman{at}eleceng.adelaide.edu.au

A new implementation for minimally redundant radix-4 SRT division with the recurrence in the signed-digit format is introduced. The implementation is developed based on the comparison multiples idea. In the proposed approach, the quotient digit's magnitude is calculated by comparing the truncated partial remainder with two limited precision multiples of the divisor. The sign is determined by investigating the polarity of the truncated partial remainder. A timing evaluation using logical synthesis shows a latency of 2.34 ns for the recurrence of the proposed divider. It is ~22% less than the conventional implementation.

Key Words: SRT division • floating-point arthimetic • reduction addition


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