The Computer Journal Advance Access originally published online on June 28, 2007
The Computer Journal 2007 50(5):616-628; doi:10.1093/comjnl/bxm032
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A High-Speed Link Layer Architecture for Low Latency and Memory Cost Reduction
1 School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Shilim-dong, Kwanak-gu, Seoul 151-742, South Korea
2 School of Electronic Engineering, Soongsil University, 1, Sangdo-5-dong, Dongjak-ku, Seoul 156-743, South Korea
* Corresponding author: hjlee_paper{at}capp.snu.ac.kr
Received 20 August 2006; revised 6 May 2007
Accepted for publication 8 May 2007.
This paper presents the design and implementation of the InfiniBand link layer with special efforts made for packet latency reduction and buffer space optimization. The link layer is designed to avoid any architectural conflict while its components are executed in parallel as far as possible. For high-speed packet processing with the various quality of service supports required by InfiniBand, three candidates for packet receiving architecture are investigated. The maximum and minimum delays from an input to an output of a switch adopting each of the three candidates is estimated by mathematically modeling the switch delays. Then, the candidate architecture with the best performance is chosen, and a novel first-in first-out (FIFO) is designed to efficiently implement the chosen architecture. Simulation results show that the chosen architecture achieves the least packet latency and uses the least memory space among the three candidates. The link layer core is implemented in an InfiniBand host channel adapter system-on-chip called KINCA.
Key Words: parallel processing • network processor • VLSI design • cluster system • system-on-chip