The Computer Journal Advance Access published online on April 8, 2009
The Computer Journal, doi:10.1093/comjnl/bxp020
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization1
1 Department of Electrical and Electronic Engineering, Imperial College London, South Kensington Campus, London SW7 2AZ, UK
2 Department of Computer Science and Technology, University of Peloponnese, Tripolis, Greece
* Corresponding author: qiang.liu2{at}imperial.ac.uk
Received 14 October 2008; revised 5 March 2009
This paper describes our approaches to raise the level of abstraction at which hardware suitable for accelerating computationally intensive applications can be specified. Field-programmable gate arrays are becoming adopted as a computational platform by the high-performance computing community, but there are challenges to extract maximum performance from these devices. Unlike other approaches, our focus is on data memory organization and input–output bandwidth considerations, which are the typical stumbling block of existing hardware compilation schemes. We describe our approaches, which are based on formal optimization techniques, and present some results showing the advantage of exposing the interaction between data memory system design and parallelism extraction to the compiler.
Key Words: hardware compilation • data reuse • loop parallelization • FPGA
1 A preliminary version of this paper was presented at the BCS08Visions of Computer Science Conference, held on 22–24 September 2008.