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The Computer Journal Advance Access published online on April 10, 2009
The Computer Journal, doi:10.1093/comjnl/bxp023
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© The Author 2009. Published by Oxford University Press on behalf of The British Computer Society. All rights reserved. For Permissions, please email: journals.permissions@oxfordjournals.org

Verifying a Synthesized Implementation of IEEE-754 Floating-Point Exponential Function using HOL

Behzad Akbarpour1,*, Amr T. Abdel-Hamid2, Sofiène Tahar3 and John Harrison4

1 University of Cambridge, Computer Laboratory, William Gates Building, 15 JJ Thomson Avenue, Cambridge CB3 0FD, UK
2 German University of Cairo, Faculty of Information and Electronics Technology, Tagamoa El-Khamis, Cairo, Egypt
3 Concordia University, Department of Electrical and Computer Engineering, 1455 De Maisonneuve Blvd. West, Montreal, Quebec, Canada, H3G 1M8
4 Intel Corporation, JF1-13, 2111 NE 25th Avenue, Hillsboro, Oregon, OR 97124, USA

* Corresponding author: behzad.akbarpour{at}cl.cam.ac.uk

Received 8 January 2008; revised 16 March 2009

Deep datapath and algorithm complexity have made the verification of floating-point units a very hard task. Most simulation and reachability analysis verification tools fail to verify a circuit with a deep datapath like most industrial floating-point units. Theorem proving, however, offers a better solution to handle such verification. In this paper, we have hierarchically formalized and verified a hardware implementation of the IEEE-754 table-driven floating-point exponential function algorithm using the higher-order logic (HOL) theorem prover. The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, starting from gate-level implementation of the circuit up to a high-level mathematical specification.

Key Words: floating-point arithmetic • formal hardware verification • higher-order logic • theorem proving

Handling editor: Iain Stewart


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