The Computer Journal Advance Access published online on May 4, 2009
The Computer Journal, doi:10.1093/comjnl/bxp036
A Cascadable Random Neural Network Chip with Reconfigurable Topology
1 ON Semiconductor, Automotive and Power Group, Vilvoorde, Belgium
2 Middle East Technical University, Electrical Engineering Dep., Ankara, Turkey
3 Eastern Mediterranean University, Computer Engineering Dep., Gazi Magusa, via Mersin 10, Turkey
4 Eastern Mediterranean University, GMTGB Technopark, Gazi Magusa, via Mersin 10, Turkey
* Corresponding author: mbadaroglu{at}gmail.com
Received 3 October 2008; revised 13 February 2009
A digital integrated circuit (IC) is realized using the random neural network (RNN) model introduced by Gelenbe. The RNN IC employs both configurable routing and random signaling. In this paper we present the networking/routing aspects as well as the performance results of an RNN network implemented by the RNN IC. In the RNN model, each neuron accumulates arriving signals and can fire if its potential at a given instant of time is strictly positive. Firing occurs at random, the intervals between successive firing instants following an exponential distribution of constant rate. When a neuron fires, it routes the generated pulses to the output lines in accordance with the connection probabilities. The number of neurons in the network is programmable and could be connected to each other with any desired neuron interconnection and this connection could be changed on the fly. The RNN chip architecture is cascadable to generate any network topology. All the parts of the RNN circuit are implemented using a standard digital Complimentary-Metal-Oxide-Semiconductor (CMOS) process.
Key Words: neural networks • random neural network (RNN) • hardware • architecture; digital integrated circuits