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The Computer Journal Advance Access published online on June 9, 2009
The Computer Journal, doi:10.1093/comjnl/bxp056
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© The Author 2009. Published by Oxford University Press on behalf of The British Computer Society. All rights reserved. For Permissions, please email: journals.permissions@oxfordjournals.org

Fine-Grain Register Allocation and Instruction Scheduling in a Reference Flow1

Dae-Hwan Kim and Hyuk-Jae Lee*

School of Electrical Engineering and Computer Science, Seoul National University, #054, 599 Gwanangno, Gwanak-Gu, Seoul 151-744, Korea

* Corresponding author: hyuk_jae_lee{at}capp.snu.ac.kr

Received 8 July 2008; revised 16 March 2009

This paper proposes a new register allocation technique in which register allocation is performed at every reference of a variable. For each reference, the costs of various possible register allocations are estimated by tracing a possible instruction sequence. A cost model is formulated to reduce the scope of tracing. With an extension of the cost model to the estimation of instruction execution time, a new technique for the integration of instruction scheduling and register allocation is also proposed. Experiments show that the proposed register allocation and the integration techniques achieve significant improvements when compared with widely used existing techniques.

Key Words: compiler • register allocation • instruction scheduling • spill code • variable reference flow graph

Handling editor: Gelenbe, Erol

1 A part of Sections 4–6 is presented at the 6th International Workshop on Embedded Computer Systems: Architectures, Modeling and Simulation.


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