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The Computer Journal 1987 30(3):283-285; doi:10.1093/comjnl/30.3.283
© 1987 by British Computer Society
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Short Note

A Design for an Efficient NOR-gate only, Binary-ripple Adder with Carry-completion-detection Logic

D. Salomon *

Computer Science Department, California State University, Northridge, CA 91330, USA

A novel way of designing a ripple-carry adder is presented. The new design uses only NOR gates. It is both economical, using only six NOR gates per stage, and efficient, since a carry-completion-detection circuit can easily be integrated into it at a cost of (approximately) one NOR gate per two adder stages.

Received January 1986. revised September 1986.

* Computer Science Department, California State University, Northridge, CA 91330, USA.


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