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The Computer Journal 1990 33(3):241-246; doi:10.1093/comjnl/33.3.241
© 1990 by British Computer Society
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A New Parallel Sorting Algorithm and its Efficient VLSI Implementation

S. Dey and P. K. Srimani *

Department of Computer Science, Southern Illinois University, Carbondale, IL 62901-4511, USA

In this paper we develop a new parallel algorithm for sorting which has a time complexity of O(log n) and requires n2/log n processors. The algorithm can be readily mapped on an SIMD mesh connected array of processors which has all the features of efficient VLSI implementation. The corresponding hardware algorithm maintains the O(Log n) execution time and has a low O(n) interprocessor communication time.

Received November 1987. revised February 1990.

* Address for Correspondence: Pradip K. Srimani, Department of Computer Science, Colorado State University, Ft. Collins, CO 80523, USA.

§ Department of Computer Science, Southern Illinois University, Carbondale, IL 62901-4511, USA


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