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The Computer Journal 2001 44(6):486-503; doi:10.1093/comjnl/44.6.486
© 2001 by British Computer Society
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Managing Latency and Buffer Requirements in Processing Graph Chains

Steve Goddard1 and Kevin Jeffay2

1 Computer Science and Engineering, University of Nebraska—Lincoln, Lincoln, NE 68588-0115, USA Email: goddard@cse.unl.edu 2 Department of Computer Science, University of North Carolina at Chapel Hill, Chapel Hill, NC 27599-3175, USA

Real-time signal-processing applications for high assurance systems are commonly designed using a processing-graph software architecture. Here we demonstrate the management of latency and buffer requirements in such an architecture—the US Navy's processing graph method (PGM). By applying recent results in real-time scheduling theory to the subset of PGM employed by the US DARPA rapid prototyping of application-specific signal processors (RASSP) synthetic aperture radar (SAR) benchmark application, we identify inherent real-time properties of nodes in a PGM graph, and demonstrate how these properties can be exploited to perform useful and important system-level analyses such as schedulability analysis, end-to-end latency analysis, and memory requirements analysis. More importantly, we develop relationships between properties such as latency and buffer bounds and show how one may be traded off for the other.

Received 31 October, 2000. Revised 28 April, 2001.


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