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The Computer Journal Advance Access originally published online on February 27, 2008
The Computer Journal 2008 51(5):585-594; doi:10.1093/comjnl/bxm123
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© The Author 2008. Published by Oxford University Press on behalf of The British Computer Society. All rights reserved.For Permissions, please email: journals.permissions@oxfordjournals.org

Multiplier Evolution: A Family of Multiplier VLSI Implementations

Glenn Colón-Bonet1,3,* and Paul Winterrowd, Jr2,3

1 Intel Corporation, Mailstop TEC1-1, 4701 Technology Pkwy, Fort Collins, CO 80528, USA
2 University of Idaho, Center for Advanced Microelectronics and Biomolecular Research, 721 Lochsa Street, Suite 8, Post Falls, ID 83854, USA
3 Formerly employed by Hewlett Packard Company, 3400 E. Harmony Road, Fort Collins, CO 80528, USA

* Corresponding author: glenn.t.colon-bonet{at}intel.com

This paper provides an overview of four floating point multiplier implementations spanning microprocessor designs from 1992 to the present. The algorithm of each multiplier is explored in detail, and key measures of area, delay and design complexity are compared. The approaches span from a simple linear array to a full tree-based network, each targeted at efficient very-large-scale integration implementation. The designs show a progression of implementation techniques encompassing a 20x increase in multiplier performance during this time period.

Key Words: Digital arithmetic • floating point arithmetic • microprocessors • multiplication


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