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The Computer Journal Advance Access published online on December 19, 2005
The Computer Journal, doi:10.1093/comjnl/bxh157
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© The Author 2005. Published by Oxford University Press on behalf of The British Computer Society. All rights reserved. For Permissions, please email: journals.permissions@oxfordjournals.org
Received May 10, 2005
Revised August 24, 2005

Article

Instruction Level Parallelism through microthreading--A Scalable Approach to Chip Multiprocessors

Kostas Bousias 1, Nabil Hasasneh 2, and Chris Jesshope 1 *

1 Department of Computer Science, University of Amsterdam, NL
2 Department of Electronic Engineering, University of Hull, UK

* To whom correspondence should be addressed.
Chris Jesshope, E-mail: Jesshope{at}science.uva.nl


  Abstract

Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction level parallelism (ILP). The most significant problem with this approach is a large instruction window and the logic to support instruction issue from it. This includes generating wake-up signals to waiting instructions and a selection mechanism for issuing them. Wide-issue width also requires a large multi-ported register file, so that each instruction can read and write its operands simultaneously. Neither structure scales well with issue width leading to poor performance relative to the gates used. Furthermore, to obtain this ILP, the execution of instructions must proceed speculatively. An alternative, which avoids this complexity in instruction issue and eliminates speculative execution, is the microthreaded model. This model fragments sequential code at compile time and executes the fragments out of order while maintaining in-order execution within the fragments. The only constraints on the execution of fragments are the dependencies between them, which are managed in a distributed and scalable manner using synchronizing registers. The fragments of code are called microthreads and they capture ILP and loop concurrency. Fragments can be interleaved on a single processor to give tolerance to latency in operands or distributed to many processors to achieve speedup. The implementation of this model is fully scalable. It supports distributed instruction issue and a fully scalable register file, which implements a distributed, shared-register model of communication and synchronization between multiple processors on a single chip. This paper introduces the model, compares it with current approaches and presents an analysis of some of the implementation issues. It also presents results showing scalable performance with issue width over several orders of magnitude, from the same binary code.

Keywords: concurrency; CMP; microthreads; code fragments.
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